Semiconductor memory devices that store data may be classified into volatile memory devices and nonvolatile memory devices. In contrast to volatile memory devices, nonvolatile memory devices, such as flash memory devices, retain stored data even if power is abruptly interrupted. For this reason, nonvolatile memory devices are widely employed in memory cards and other electronic devices such as mobile communication terminals.
Flash memory devices may be classified as NOR type and NAND type devices according to the structure of their cell arrays. NOR type flash memory devices may allow high speed random access, while NAND type flash memory devices may allow high speed programming and erasure operations and may be highly integrated. The performance of program and erase operations can depend upon the coupling ratio (CR) of their unit cells. A program operation is performed by Fowler-Nordheim (FN) tunneling or hot electron injection, and an erase operation is performed by FN tunneling. FN tunneling can occur when an electric field of 6 to 8 MV/cm is applied to a tunnel insulating layer between a floating gate electrode and a substrate of a cell. The electric field that is applied between the floating gate electrode and the substrate can be induced by applying a high voltage of 15 to 20 V to a control gate electrode that is on the floating gate electrode. Accordingly, the programming voltage or erasing voltage may be reduced by increasing the CR of the unit cell of the flash memory device. The CR may be expressed by the following Equation 1:
                              CR          =                      Ci                          Ci              +              Ct                                      ,                            (        1        )            
where Ci refers to the capacitance of an inter-gate insulating layer interposed between the floating gate electrode and the control gate electrode, and Ct refers to the capacitance of the tunnel insulating layer interposed between the floating gate electrode and the substrate.
As can be seen from Equation 1, the CR may be increased by increasing the capacitance Ci of the inter-gate insulating layer. A method for increasing the capacitance Ci of the inter-gate insulating layer is disclosed in U.S. Patent Publication No. 2003-0141535. A high-k dielectric layer is used in place of a silicon oxide/silicon nitride/silicon oxide (ONO) layer as an inter-gate insulating layer has been proposed to increase the capacitance Ci of the inter-gate insulating layer. However, using a high-k dielectric layer as the inter-gate insulating layer can necessitate changes in the fabrication process.
FIGS. 1A, 1B, 2A, and 2B are cross-sectional views illustrating a method of fabricating a conventional flash memory device. FIGS. 1A and 2A are cross-sectional views taken in the direction of word line patterns of the flash memory device, and FIGS. 1B and 2B are cross-sectional views taken in the direction of active regions of the flash memory device.
Referring to FIGS. 1A and 1B, an isolation layer 12 is formed in a semiconductor substrate 10 to define a plurality of active regions 14. The active regions 14 are defined as parallel lines. A tunnel insulating layer 16 is formed on the active regions 14. Thereafter, a polysilicon layer (not shown) is formed on the entire surface of the semiconductor substrate 10, including on the tunnel insulating layer 16, and patterned to form polysilicon layer patterns 18. The polysilicon layer patterns 18 are patterned as lines that cover the active regions 14 but expose the isolation layer 12.
Referring to FIGS. 2A and 2B, a high-k dielectric layer (not shown) and a control gate material layer (not shown) are formed on the semiconductor substrate 10 including on the polysilicon layer patterns 18. The high-k dielectric layer is conformally formed along sidewalls and top surfaces of the polysilicon layer patterns 18. The control gate material layer, the high-k dielectric layer, and the polysilicon layer patterns 18 are sequentially patterned to form word line patterns 24 that cross the active regions 14 and the isolation layer 12. The word line patterns 24 include floating gate electrodes 18′, an inter-gate insulating layer 20, and control gate electrodes 22, which are sequentially stacked. Typically, a patterning process for forming the word line patterns 24 is performed by sequentially etching the control gate material layer, the high-k dielectric layer, and the polysilicon layer patterns 18 using photolithography and dry etching processes. The high-k dielectric layer is etched after etching the control gate material layer. In this case, a process recipe suitable for dry etching the high-k dielectric layer has not yet been established. As a result, especially in a NAND type flash memory device in which word line patterns are spaced at small intervals, it may be more difficult to etch the high-k dielectric layer.
More specifically, the high-k dielectric layer formed on the sidewalls of the polysilicon layer patterns 18 may be not completely etched but may instead remain as high-k dielectric fences. During a subsequent process of etching the polysilicon layer patterns 18, the polysilicon layer patterns 18 adjacent to the high-k dielectric fences may not be etched. As a result, electric bridges may be formed between the adjacent floating gate electrodes 18′ along the active regions 14. However, if high-k dielectric layer is over-etched in an attempt to prevent formation of electric bridges, the polysilicon layer patterns 18 may be damaged when etching the high-k dielectric layer. Hence, during the subsequent process of etching the polysilicon layer patterns 18, the active regions 14 disposed under the polysilicon layer patterns 18 may experience etching damage.